Common-Centroid Constrained Analog Placement

In the layout design of analog integrated circuits, common centroid constraints can effectively reduce parasitic mismatch and thermal gradients, which may otherwise degrade circuit performance. In this paper, we first survey the frontline research of common-centroid-aware layout placement algorithms and implement a graph-based packing approach to handle common centroid constraints in the analog layout design. Then we develop a naïve center-based packing approach that features fast execution speed although not competitive in terms of area and dead space. By comparing both approaches above, we further propose a contour-based packing scheme that can achieve the best performance of area and dead space with slight increase in CPU time. Our experimental results demonstrate the effectiveness of the proposed scheme and validate a new direction in this area.